1. Field
Example embodiments relate to a method of manufacturing a semiconductor device.
2. Description of the Related Art
As semiconductor devices are becoming highly integrated, sizes of source/drain regions and width of gate electrodes and metal wiring in semiconductor devices are being, rapidly decreased. Thus, multi-layered wirings have been widely used as a wiring structure of the semiconductor device in which a number of wiring layers are sequentially stacked in a vertical direction and each of the wiring layers are electrically connected to each other by interconnections such as a contact plug.
In general, the wirings in a semiconductor device are electrically connected to underlying conductive structures such as transistors and are separated from each other by a number of insulation inter-layers. Then, the insulated upper and lower wirings are electrically connected to each other by the interconnections penetrating through the insulation interlayer. Recently, the interconnections may comprise a metal having low electrical resistance such as aluminum (Al), copper (Cu) and tungsten (W) as the high integration degree of the semiconductor device. Particularly, tungsten (W) has been much more widely used for the interconnection than any other metals because of high quality of step coverage and high pattern facilitation.
Metals are generally formed into the wiring structure for a semiconductor device by a deposition process and the deposition process usually requires chemical reactions at a high temperature. Thus, while performing the deposition process, various barrier layers are provided between the insulation interlayer and the interconnection for preventing the damage to the insulation interlayer and the underlying conductive structures.
Particularly, tungsten (W), which is now most widely used as a contact plug in a semiconductor device, has poor adherence to the insulation interlayer most of which comprises oxides. In addition, tungsten source gases in the deposition process usually cause damage to sidewalls of a contact hole or a via-hole. The barrier layer usually includes a glue layer for compensating the poor adherence to the insulation interlayer and an anti-diffusion layer for preventing fluorine ions (F—), byproducts of the fluorine source gases of the deposition process, from diffusing into the insulation interlayer. For example, a multilayered structure of titanium and titanium nitride (Ti/TiN), tungsten and tungsten nitride (W/WN) or tantalum and tantalum nitride (Ta/TaN) is widely used as the barrier layer. W/WN structure is used as the barrier layer because a tungsten (W) plug can be formed continuously with the W/WN barrier layer and a contact resistance between the barrier layer and the contact plug can be reduced.
Various deposition processes based on chemical reactions of source materials have been utilized for forming the WN layer that is conformal with the profile of the contact hole or the via hole and has high quality of step coverage.
Particularly, it has been suggested in U.S. patent application Ser. No. 12/183,421 by the assignee of this application that a number of unit processes for forming the barrier layer be performed in a single process chamber having a number of heaters in place of using a respective process chamber, which may prevent a vacuum break between consecutive unit processes caused by process chamber change to thereby increase layer quality.
For example, the glue layer, functioning as an ohmic layer in a wiring structure, is formed at a first process unit of a single process chamber and the anti-diffusion layer is formed at a second process unit of the single process chamber. Thereafter, the metal plug is formed at a third process unit of the same single process chamber by a deposition process to thereby complete the wiring structure for the semiconductor device.
However, various unit processes for forming the barrier layer are performed in the same single process chamber, thus the source gases for the respective unit process are difficult to supply into the single process chamber to thereby increase the sheet resistance of the deposited layer and to maintain thickness uniformity of the deposited layer.